Experience: 4+ years (Intermediate to Senior)

About the Role

In this role, you will focus on layout extraction and physical verification for advanced SoC designs, working with cutting‑edge tools and large-scale chip projects.

• Develop and maintain automated signoff flows for layout extraction
• Perform Parasitic Extraction (PEX) using industry tools
• Work with tools such as Siemens Calibre or Synopsys StarRC
• Troubleshoot LVS (Layout vs. Schematic) issues
• Automate workflows using scripting (Python, Perl, Tcl)

Requirements (Must‑Have)

• 4+ years of experience in physical design / design automation
• Strong hands‑on experience with:
  • Siemens Calibre or Synopsys StarRC
• Solid understanding of:
  • Layout extraction (PEX)
  • LVS verification
• Experience with scripting (Python / Perl / Tcl)
• Familiar with semiconductor design flow a...