Design Verfication Technical Lead

Kuala Lumpur, Malaysia | Posted on 02/26/2026

• Country Malaysia

Job Description

• Develop testbench components such as test, sequence libraries, bfm and monitor by usingobject oriented programming verification techniques following UVM methodology
  
• Automate validation environment to improve activities such as test writing, regressionrunning or coverage collection
  
• Define detailed testplan from specification by working with architects and design engineers
  
• Write and debug tests in UVM/C++
  
• Incorporate function/code-coverage, assertions, cover-groups etc to achieve 100% verificationcompleteness prior to tapeout
  
• Experience in PCIe/Ethernet/DDR/USB will be a plus
  
• Train up juniors in the validation team
  

Requirements

• Knowledge in C, Python, shell scripting
  
• Great interpersonal and communication skills

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