Job Location : Pune

Qualifications : BTECH/MTECH

Job Description:

• Should have good post silicon DFT bringup and debug experience.
• Hands on in multi-vendor DFT tools.
• Create test plan for complex ASICs and drive the DFT implementation.
• Ability to guide people, multiplex many issues and set priorities.
• Strong hands-on experience with Synopsys SMS tool/Cadence Tools
• Capable of handling block-level and top-level MBIST activities