DFX Architect

As a DFX Architect, you will be the technical authority for Altera’s next‑generation FPGA and SoC families, defining the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world‑class quality, minimize Test Cost (TCO), and accelerate Time‑to‑Market (TTM).

Key Responsibilities

• Architectural Strategy: Define and document DFX architectures for multi‑die (chiplet) systems, high‑speed transceivers, and massive FPGA fabrics.
• Technology Leadership: Drive the adoption of advanced DFX features such as IEEE 1687 (IJTAG), IEEE 1838 (3D‑IC), and High‑Speed Link Testing (HSLT).
• Test Cost Optimization: Develop strategies to reduce Test Data Volume (TDV) and Test Application Time (TAT) through advanced compression and adaptive testing techniques.
• Debug Architecture: Lead the definition of on‑chip debug infrastructures (logic analyzers, trace buffers, and scan‑dump) to enable rapid root‑cause ...