Job Overview As a E5/MTS/SMTS NAND Design Rule / Process Integration engineer, your role is to support the development and high-volume manufacturing of advanced 3D NAND technologies. This role drives design-rule and PDK deliverables, partners closely across process integration and design organizations, and ensures quality, documentation, and timely execution across R&D and production programs.
Responsibilities
- Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.
- Own program execution and milestones from kickoff through end-of-life.
- Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
- Ensure high quality and documentation for Design Rule Checks (D...