We are seeking an R&D engineer to design and physically implement high-performance System‑On‑Chip ASICs. The role requires leading teams in physical design of large ASICs (500‑800 million gates) and providing technical support to customers.

• Key competencies required:
  • Leading team in physical design implementation of large ASICs (500‑800 million gates).
  • Providing technical support and managing customer relationships.
  • Hands‑on competency in leading edge physical design EDA tools.
  • In‑depth knowledge of CPU/DSP architecture and related physical design implementation.
  • Collaborating with RTL and Physical Design teams to resolve timing violations.
• Utilize commercial and in‑house EDA tools for design and implementation of 500‑800 million gate integrated circuits in 5 nm / 3 nm / 2 nm process technologies.
• Participate in innovation, design flow and methodology deve...