Position Overview: The High-Density Flash team supplies Non-Volatile Memory (NVM) IP’s to numerous SoC groups within the company.These IP’s include analog macro cells and sophisticated digital controllers. We are seeking a highly skilled and experienced Design Verification Engineer to drive verification of our digital controllers and for test chips using our NVM IP. The ideal candidate will have a strong background in digital verification, digital design, and an understanding of memory and NVM technologies. As a team member, you will help deliver robust integrated NVM designs which meet functional, performance, power, and reliability goals. Key Responsibilities: Technical: Develop test plans to fully verify IP functionality and features, working with IP digital and analog designers, SoC designers, and the NVM IP test team Implement test methodologies including Verilog/System-Verilog testbenches, constrained-random and directed tests, assertion-based checking, coverage metrics and clock...