Key Responsibilities: Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis and design documentation Key Requirements: Master/Degree in Electrical Engineering with 3 years of ASIC design experience preferred Familiar with ASIC design flow, Cadence digitalimplementation & verification tools Experience in RTL coding based on Verilog.Familiar with the digital simulation debugging environment Familiar with UNIX/Linux environment andscripting A team player with good communication skills Able to work independently, flexible, andcreative Strong analytical and problem solving