Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

Job Responsibilities:

• Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
• Develop and execute verification plans, including testbench development using UVM methodology.
• Perform functional verification, debugging, and coverage analysis to ensure design correctness.
• Participate in SoC integration, testability (DFT) design, and overall front-end development flow.
• Collaborate with architecture, physical design, and software teams to ensure seamless integration.
• Contribute to automation and tooling improvements using scripting languages.

Job Requirements:

• Bachelor's degree or above in Electrical Engineering, Computer Engineering, or related fields.
• Understanding of digital design fundamentals and IC development flow.
• Familiarity with Verilog/SystemV...