Job Title: Physical Design Engineer (PD/PnR)

Location: Bay Area / Austin (Hybrid

Job Summary

Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs.

Key Responsibilities

• Perform block-level and top-level Physical Design implementation using Fusion Compiler.

• Drive floorplanning, placement, CTS, routing, and timing closure.

• Execute and analyze Static Timing Analysis (STA) across multiple corners and modes.

• Implement and verify low-power designs using UPF, including isolation, level shifters, retention, and power domain checks.

• Support physical signoff activities such as DRC, LVS, IR drop, and EM analysis.

• Collaborate with RTL, DFT, Power, and Signoff teams to achieve PPA...