Principal Design Engineer (SystemVerilog / Micro-Architecture) – £100,000–£135,000 + bonus
My client’s engineering team is looking to add Principal Design Engineers to support the development of next-generation GPU / AI compute IP.
This role is focused on strengthening core design and micro-architecture capability , with a clear objective of unblocking delivery across critical programmes where design is currently the constraint.
You will operate at the intersection of architecture, RTL design, and physical implementation awareness , working closely with verification and system teams to ensure scalable, high-performance silicon delivery.
Principal Design Engineer – Role & Responsibilities:
Develop high-quality SystemVerilog RTL aligned to performance, power, and area targets
Work closely with verification teams to ensure design-for-verification efficiency
Collaborate with physical design teams to understand and mitigate timing, congestion, and power...