Join Ciena as a Senior ASIC Engineer, focused on developing cutting‑edge Digital Signal Processing technology. Your expertise in synthesis and static timing will be pivotal for frontend implementation. As part of Ciena’s cutting‑edge team, you will have a profound impact on the frontend design of industry‑leading ASICs.

This role requires experience in static timing analysis and logical equivalence verification, ensuring high‑performance outcomes. Collaboration with various engineering disciplines and external partners will drive project success.

Key Responsibilities

• Oversee frontend implementation for assigned IPs
• Maintain timing constraints for integration signoff
• Validate logical equivalence through various stages
• Collaborate on ASIC integration and design activitiesEnhance automation with scripting tools

Requirements

• B.Sc. in Electrical or Computer Engineering
• Experience in ASIC synthe...