We are seeking a skilled Design Verification Engineer to drive the functional verification of semiconductor IPs and SoC platforms. The role involves developing robust verification environments, executing comprehensive test plans, and ensuring high-quality design signoff through thorough validation and coverage closure.

Key Responsibilities

• Develop and maintain verification environments using SystemVerilog and UVM methodologies.
• Create detailed verification plans and test strategies based on design specifications.
• Execute regression suites, analyze results, and debug failures.
• Develop and utilize assertions to improve verification quality.
• Perform functional and code coverage analysis and drive coverage closure.
• Verify complex protocols and interfaces (e.g., PCIe, DDR, USB, Ethernet).
• Collaborate with design, architecture, and validation teams to resolve issues.
• Support verification signo...