Position OverviewLayout Design Engineer – HBM Team, Guadalajara, Mexico.ResponsibilitiesDesign and development of analog, mixed-signal, custom digital block and full chip level integration support.Perform layout verification like LVS/DRC/Antenna, quality check and documentation.Responsible for on‐time delivery of block‐level layouts with acceptable quality.Lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple‐project environment.Effectively communicate with Global engineering teams to assure the success of layout project.Minimum Qualifications5+ years of experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
BE or MTech in Electronic/VLSI Engineering, or related.Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS is a must.Hands‐on experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Gene...