A cutting-edge semiconductor company in Zürich is seeking a Lead ASIC Physical Design Engineer to own the backend implementation capability. This senior role involves defining RTL-to-GDSII strategy, driving implementation challenges, and leading a team. Ideal candidates will have over 10 years in ASIC design, experience with Synopsys or Cadence toolchains, and a strong background in power optimization and timing closure. The position offers a hybrid work model, fostering innovation and technical growth.
#J-18808-Ljbffr