Principal Accountabilities: (the 6-8 main areas of responsibility)

· Develop verification plan based on chip specifications.

· Setting up of Digital Verification flow for Full Chip, from scratch and ensure Spec Compliance.

· Design and develop verification systems, decomposition and hardware/software partitioning with focus on reuse and scalability

· Design of optimized digital blocks/verification components meeting functional, cost and low power constraints and ensure spec compliance.

· Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.

· Support DFT strategy and implementation.

· Verification planning, feature extraction and verification test case development.

· Interface with P & R for digital hand-off and post layout verification.

· Develop test vectors for production test.

· Perform physical silicon device evaluation where necessary...