KEY RESPONSIBILITIES:

• Contribute to IP selection and architecture definition; create functional specifications.
• Perform PPA evaluation and optimization. Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR.
• Support debugging across RTL simulation, gate-level, and post-layout simulations.
• Conduct quality checks using FE EDA tools such as Spyglass.lint, CDC, RDC, etc.
• Take ownership of the full project lifecycle, from architecture to production.

PREFERRED EXPERIENCE:

• > 10 years of hands-on experience in digital frontend design.
• Strong proficiency in Verilog/VHDL.
• Hands-on experience with logic FE tools (e.g., VCS, Verdi, Spyglass, DC).
• Experience in Static Timing Analysis is a strong plus.
• Prefer candidates with experience implementing advanced-process chips.
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