Altera is looking for a Senior Static Timing Analysis Engineer to enhance FPGA designs in Toronto, Ontario. Focus on timing closure, debugging violations, and collaborating with cross-functional teams for optimal performance.

In this pivotal role at Altera, you will perform static timing analysis and assist in timing closure efforts for FPGA designs. Candidates should have over six years of experience in STA, a firm grasp of design flows, and a collaborative spirit to interact with various engineering teams. Your contributions will include developing timing constraints and improving design methodologies.

Key Responsibilities: • Execute static timing analysis for FPGA designs • Debug timing violations collaboratively with design teams • Develop and validate timing constraints accurately • Improve timing convergence with architecture teams • Contribute to automation and flow enhancements

Requirements: • 6+ years in Static Timing Analysis for ASIC/FPGA • Strong ...