We are looking for a veteran digital architect who can own and drive the digital subsystems of our next‑generation 112 Gb/s‑and‑beyond Ethernet SerDes. This role collaborates closely with analog, DSP, firmware, and SoC teams, translating high‑level requirements into clean RTL that meets power, performance, and area (PPA) targets—and also guides the design through synthesis, STA, and physical implementation.

Responsibilities

• Define and document the digital micro‑architecture for PMA/PMD/PCS blocks, including DSP datapaths and control processors.
• Write high‑quality Verilog RTL, verify it (directed + UVM), and debug corner cases across multiple asynchronous clock domains.
• Collaborate daily with analog designers to understand and model mixed‑signal effects, ensuring robust digital‑on‑top flows.
• Craft timing constraints, run STA, and close timing in cutting‑edge FinFET nodes.
• Drive lint/CDC/RDC clean‑up and formal checks....