This engineer plays a key role in SoC Design flow, he/she will mainly focus on DFX SMS design, verification and post-silicon ATE pattern debug tasks. Moreover, he/she is expected to provide strong technical supports for Feint, PD, SoC DV and other DFX functional domain owners.

THE PERSON

Good team worker with solid mbist design and verification experience. Knowledge reservation on STA/Verification/RTL quality check will be a strong plus.

KEY RESPONSIBILITIES

• Implement SoC DFX SMS design on SRAM, ROM, Latch Arrays, etc.
• Develop and verify tile level and chip level bist and memory repair test cases.
• Develop and verify high coverage and cost-effective test patterns for production test.
• Support DFX SMS design quality check and documentation tasks.
• Support DFX silicon bring up and ATE test.

PREFERRED EXPERIENCE

• Solid background on process, device or ASIC design.
• ...