Responsibilities

1. Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
2. RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
3. Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
4. Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
5. Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, an...