Job Highlights Positive team atmosphere, Career growth opportunity, Paid leave, 100+ mil users, Meals provided, Competitive compensation
Responsibilities - Verification Planning: Deeply analyze architecture and design specifications to develop comprehensive and high-coverage module-level, subsystem-level, or SoC system-level Test Plans.
- Environment Development: Build from scratch or maintain highly reusable and automated advanced verification environments (Testbench) and components (Scoreboard, Monitor, Sequence, etc.) based on UVM methodology.
- Test Execution & Closure: Develop high-quality testcases, execute Constrained Random and Directed tests, and drive Functional and Code Coverage to 100% closure.
- System‑Level Verification: Responsible for Gate‑Level Simulation (GLS) and SDF back‑annotated timing simulation. Assist in FPGA prototyping and Hardware/Software co‑debugging on Emulation platforms (e.g., Palladium/ZeBu).
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