Job Description1. Work on 7nm~3nm physical design implementation, methodology, and sign-off
2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification
3. Manage schedule, resolve design and flow issues, drive methodologies and execution

#LI-LL1Requirement1. MS +2yrs in EE/CS
2. APR/Signoff hands-on and tapeout experience in deep submicron technology
3. Tcl/Perl/script/C/C++ programming skills
4. Strong communication skills