STA Lead

Location: Bengaluru, India

Experience: 6–10 Years

Role Overview

We are seeking a highly skilled STA Lead to drive timing closure and signoff for complex SoC, CPU, AI/ML, and high-performance computing designs at advanced technology nodes. This is a hands-on technical role focused on timing analysis, signoff quality, methodology development, and achieving first-pass silicon success.

Key Responsibilities

• Own block and subsystem-level STA closure from synthesis through signoff.
• Drive timing budgeting, constraints development, MCMM analysis, and timing convergence.
• Analyze and resolve setup/hold, OCV/AOCV/POCV, CRPR, crosstalk, CDC, and timing ECO challenges.
• Collaborate closely with RTL, synthesis, physical design, CTS, SI, and signoff teams to achieve timing closure.
• Support timing signoff reviews and tape...