1. Advanced CMOS PLL architecture definition, device level design and verification.

3. Lead layout implementation and testing.

4. Achieve industry leading jitter, noise and spur performance.

5. Architecture and system level design.

• Architecture choice-based noise/jitter/spur spec (optimal architecture - integer/Fraction/SS/MDLL etc.)
• Derive system parameters (Loop BW, Noise margin, noise TF, spur reduction), system verification through behavioral to transistor model (Verilog-A, MATLAB, SpectreRF.
• Design and verify key components: LC VCO, R-VCO, MMD, PFD, CP, LF, frac-N SDM, calibration engine and LDO.
• Noise optimization (sub 100fs RMS jitter), wide tuning range (multi-GHz), low power and PVT robustness.
• Calibration logic (ADC based VCO gain tracking, background spur reduction, DTC linearization).

7. Layout and physical implementation.

• Lead layout floor planning, strategize ...