Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has a strong foundation in STA, experience with modern design flows, and the ability to work effectively in a collaborative engineering environment. Key Responsibilities

Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing sign‑off support. Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams. Assist in developing and validating timing constraints to ensure accurate modeling of design intent. Work closely with design, architecture, and implementation teams to improve timing convergence. Apply established STA methodologies and contribute to flow improveme...