We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks, along with hands‑on experience using industry‑standard EDA tools on advanced technology nodes.
Key Responsibilities
- Perform Static Timing Analysis (STA) at block‑level and/or full‑chip level using industry‑standard tools
- Develop, analyze, and validate timing constraints (SDC) including clocks, generated clocks, IO constraints, and exceptions
- Drive timing closure across synthesis, PnR, and signoff stages
- Analyze and resolve setup, hold, transition, capacitance, crosstalk, and logical DRC violations
- Work closely with Physical Design, Synthesis, and Clocking teams to fix timing issues using ECO techniques