UST is seeking a skilled engineer in Bayan Lepas, Malaysia, to manage the physical design flow from RTL to GDSII delivery. The ideal candidate will have a Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering, along with 2–5+ years of experience in physical design and proficiency in tools like Synopsys and Cadence. Responsibilities include clock distribution network design, layout verification, and optimization for power and performance.
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