• BSc in Electronics engineering/communication system engineer/ Computer Engineering from a leading University.• 8+ years of experience as a VLSI Designer – including writing and ownership on a complex Verilog blocks for ASIC with tight frequency, area and power requirements.• 3+ years of experience in leading a design team. • Working on a full design flow from high-level architecture definitions, through micro ARCH, Verilog writing and verification process up to timing closure and STA.